RAMBUS DDR4 4*(64bits+8ECC) practice in 12LP

Die size is 20mm x 20mm

2.5D package

3 level of hierarchies

Crossbar hardened and reused by 50+ times

DDR4 hardened in 2 blocks

Each block contains 2*(64bits+8ECC)

64 DQ share 1 CA, and 128bits share 1 controller

The critical path is on boundary timing budgeting and closure: more than 3000 Flip-flop need to be determined physical location considering both DDRPHY and controller internal timing

Synopsys DDR4 needs to be hardened

CLAMP, DECAPVDDQ and DECAPVDDLP needs to added and verified

Special electrical and timing check between MASTER and DBYTE

Manually placement and routing by special rules